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[VHDL-FPGA-Verilog] s29gl128n

Description: 128Mbit Flash Memory
Platform: | Size: 17408 | Author: rillyxue | Hits:

[VHDL-FPGA-Verilog] VHDLsample

Description: 英国诺森比亚大学的vhdl语言例程集锦，英文原版。 包含很多优秀的VHDL语言范例，可供学习。所有程序均可在符合IEEE标准的模拟器上模拟。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be synthesised using current synthesis tools.
Platform: | Size: 172032 | Author: eensy | Hits:

[Other] dualportram_vhdl

Description: 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware description language using the dual-caliber RAM block memory initialization
Platform: | Size: 2048 | Author: sharbel | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于vhdl的各种存储器描述，实现存储器功能-Vhdl description based on a variety of memory to achieve the memory function
Platform: | Size: 24576 | Author: wuwugui | Hits:

[VHDL-FPGA-Verilog] ad574

Description: vhdl编写，完成了对ad芯片ad574的控制，并将转化的数据存于fpga的内部存储器中，然后在发送出去。-vhdl prepared, completed ad control chip ad574, and conversion of data stored in the fpga internal memory and then sent.
Platform: | Size: 354304 | Author: xxhlshe | Hits:

[VHDL-FPGA-Verilog] lab5_u07_keypad_lcd_intr

Description: To understand how a keypad functions a raster scan input device and to learn how to interface a keypad to a microprocessor. • To understand how to control an LCD panel and to interface it to a microprocessor. (Normally, an LCD can be used directly as a memory-mapped I/O device, but due to current limitations of the 68HC12, a buffer will be used between the 68HC12’s data bus and the LCD panel.)-To understand how a keypad functions as a raster scan input device and to learn how to interface a keypad to a microprocessor. • To understand how to control an LCD panel and to interface it to a microprocessor. (Normally, an LCD can be used directly as a memory-mapped I/O device, but due to current limitations of the 68HC12, a buffer will be used between the 68HC12’s data bus and the LCD panel.)
Platform: | Size: 40960 | Author: shay | Hits:

[VHDL-FPGA-Verilog] memory

Description: memory design vhdl code
Platform: | Size: 2048 | Author: ashwini karanjawane | Hits:

[VHDL-FPGA-Verilog] Audio_Reader_Flash_DE2

Description: This an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.
Platform: | Size: 76800 | Author: Minimus | Hits:

[Video Capture] CCD

Description: 本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.
Platform: | Size: 12288 | Author: 申永帅 | Hits:

[VHDL-FPGA-Verilog] virtex5

Description: Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins.-Virtex-5 FPGA Configuration User Guide,Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins.
Platform: | Size: 1579008 | Author: leilei | Hits:

[VHDL-FPGA-Verilog] keypadinterfacecontroller

Description: 设计并实现一个4X8键盘接口控制器，含有时序产生电路、键盘扫描电路、弹跳消除电路、键盘译码电路、按键码存储电路、显示电路。要求：当按下某一键时，在数码管上显示该键对应的键值-Design and implement a 4X8 keypad interface controller, with timing generator circuit, the keyboard scanning circuit, bounce elimination circuit, the keyboard decoder circuit, the key code memory circuit, display circuit. Requirements: When you press a key, the LED display key corresponding to the key
Platform: | Size: 6144 | Author: zhuimeng | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware description language phase accumulator, phase modulator, sine, square, triangle wave, the four independent ECG waveform memory, and describe the frequency control, phase control word, control unit and the waveform amplitude switching and other related functional units.
Platform: | Size: 4096 | Author: kelly | Hits:

[VHDL-FPGA-Verilog] CPU-Project

Description: CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.
Platform: | Size: 3383296 | Author: ilmf | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is currently executing instruction stored in the instruction register IR. Arithmetic Logic processor instructions and instructions only access memory instructions).
Platform: | Size: 4740096 | Author: jinxf | Hits:

[VHDL-FPGA-Verilog] ROM-FOFO

Description: ROM,FIFO，寄存器等各种存储器VHDL语言实现，已经用FPGA下载实现了-ROM, FIFO, registers and other memory VHDL language has been implemented with the FPGA Download
Platform: | Size: 4096 | Author: 张新 | Hits:

[VHDL-FPGA-Verilog] DianTiKongZhiQi-VHDL

Description: 电梯控制器VHDL程序，包含记忆，上升，下降，停站等功能，以及超载，故障后报警功能.rar-Elevator controller VHDL program, including memory, up, down, stop and other functions, and overloading, failure alarm. Rar
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] doc

Description: BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this project, the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. In this project, it has been demonstrated that accumulator based compaction scheme
Platform: | Size: 243712 | Author: sreekanth p | Hits:

[VHDL-FPGA-Verilog] nansflash

Description: NANDFlash存储器作为一类非易失性存储器，具有功耗低、读写快、容量大、成本低、抗震性好等优点而被广泛应用于各种嵌入式系统。 - The NANDFlash memory takes a kind of nonvolatile storage, has the power loss to be low, the read-write is quick, the capacity is big, the cost is low, the anti-knocking property good and so on merits are widely applied in each kind of embedded system.
Platform: | Size: 3566592 | Author: 刘颖 | Hits:

[VHDL-FPGA-Verilog] cunchuqi-vhdl

Description: 存储器接口VHDL程序，我已经通过仿真平台验证，希望对大家有所帮助。-Memory interface VHDL program, I have verified through the simulation platform, we want to help.
Platform: | Size: 6073344 | Author: luogang | Hits:

[VHDL-FPGA-Verilog] c4gx_f896_host_ddr2a_odt

Description: ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码-ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code
Platform: | Size: 648192 | Author: liyilang | Hits:
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